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College of Engineering and Computing

WiNoC Channel Modeling & Multiple Access

Future integrated circuits (ICs) will contain many processing cores—hundreds to thousands—and presently employ exclusively wired links to connect cores. As the number of cores grows, wire dimensions shrink, creating larger resistances. Routing of wires between cores also consumes valuable chip area, and for communication between “distant” cores, multiple links (hops) must be used, increasing communication latency. To alleviate these problems, wireless networks on chips (WiNoCs) are being investigated. Such WiNoC networks will have dimensions ~ a few cm (“attocells”), and will require data rates ~ 10 Gbps per link. Such small wireless networks present many engineering challenges. In this project we are evaluating multiple antenna designs and characterizing the WiNoC wireless channels. We are also designing effective multiple access schemes.


National Science Foundation, NSF